Multi-port devices support collision detection to flag any coincident memory accesses, also known as collisions, between independent ports that can possibly result in corrupt or unexpected data being accessed from them. For example, in a dual-port memory, if port A is reading location x000 and port B is writing to the same location at the same time, data read on port A may be incorrect. The collision detection operates by identifying timing for each port's access to the memory and raising a flag to each port whenever it sees a possibility of data corruption. In a synchronous memory, each clock cycle is divided into two sections. In the first part, the memory is accessed and in the later part, the memory recovers and gets ready for next access.
Since no blocking of writes is performed through collision detection, a reading port is always flagged (named BUSY flag) irrespective of its arrival with respect to a writing port. In the earlier example, port A will always be flagged as reading possibly corrupt data. FIG. 1 is a timing diagram 100 illustrating a write-read condition with overlapping memory access. CLK represents the respective port's clock, ADDR is the address bus, RW is read when high and is write when low, and BUSY is an active-low output collision flag. CLK, ADDR, and RW are inputs per port, while BUSY is an output. All signals are synchronous with respect to their own port's clock. For a given port, the address and read/write control at the rising edge of the port's clock is used by the memory. In the case of FIG. 1, a collision between ports A and B is experienced at the second rising edge of CLK_A at memory address MATCH. Since port A is reading and port B is writing, port A is flagged BUSY.
If both ports are writing, the choice becomes more involved. If both writing ports access the memory core at the same time, data may not belong to any specific port in that location. In this case, both ports are flagged. FIG. 2 shows a timing diagram 200 illustrating a write-write condition with overlapping memory access. ACCESS is the internal memory access pulse. When this signal is high, internal memory access is occurring and when low, the previous access is completed and the memory is recovering. “Collision” shows the overlap of internal memory access pulses of port A and port B for the memory address MATCH. Since both ports are writing, both ports are flagged BUSY. Furthermore, when memory accesses are non-overlapping but the clock cycle times are violated (both ports access the same address with overlap in cycle time), the earlier port is flagged.
However, conventional technology does not allow for collision detection to be deterministic. That is, it is not capable of signaling to the system, user, etc., specifically where the collision occurred and during what particular clock cycle. This is due to the fact that previous detection mechanisms use sequential elements (e.g., flip-flops) clocked by that port's clock to capture the BUSY flag. Since a flip-flop has a requirement of both a setup time and a hold time, it might not capture the desired value in the same cycle if either requirement is violated. Since the input signal for the flip-flop is generated by comparing addresses from independent asynchronous domains (ports), the capture of this signal is not guaranteed if it changes with respect to the other port's clock. Therefore, there is a degree of uncertainty as to during which cycle a collision actually occurred. FIG. 3 shows a timing diagram 300 for the write-write condition with overlapping clock cycles described above. In this case, the detection of the collision may not be deterministic using previous technology.
For example, if port A wrote to location x0000 and port B is writing the same location with cycle time overlap, port A will be flagged. However, if port B starts writing x0000 just when port A's cycle is ending (cycle overlap time is small), it may be possible that port A's flag is not asserted or, in worst case, is not at a specific logic voltage level for an extended amount of time (also known as meta-stable condition). As described above, this condition has a setup time requirement for the later arriving port with respect to the end of the cycle of the earlier arriving port in order to detect a collision. This scenario is likely to violate the setup time requirement. Since collision detection needs to operate for successive cycles, a standard logic synchronizer would have resolved the meta-stability issue, but a cycle of uncertainty would persist nonetheless. For example, when a port is flagged through a 2-stage synchronizer, it is not possible to state whether the collision occurred 2 cycles prior or 3 cycles prior. Thus, the collision detection is indeterminate.